One type of a conventional D-RAM comprises a plurality of memory cells formed on a semiconductor substrate. Each of the memory cells comprises a transfer transistor and a trench-shaped capacitor. A gate of the transfer transistor is connected to a word line of the D-RAM, and a drain thereof is connected to either a bit line or a reference bit line which transfers a reversed signal of the bit line. A source of the transfer transistor and one terminal of the trench-shaped capacitor are formed as one unit. A potential level of the other terminal of the trench-shaped capacitor is fixed at a predetermined level. The bit line and the reversed bit line are connected to a sense amplifier in which a difference of a potential level between the bit line and the reference bit line are amplified. The semiconductor substrate is fixed at a ground level or at a reversed bias level.
In writing operation of data into the memory cell, the word line becomes high (equal to or over V.sub.cc) to provide an ON state of the transfer transistor, so that a potential level of the bit line, which is either high (V.sub.cc) or low (GND), is transferred to the trench-shaped capacitor through the transfer transistor. After the writing operation, the word line becomes low to provide an OFF state of the transfer transistor, so that the trench-shaped capacitor is cut off from the bit line to maintain a predetermined potential level.
In reading operation of data from the memory cell, the word line becomes high to provide an ON state of the transfer transistor on condition that the bit line and the reference bit line are at a floating state having a predetermined potential level (1/2 V.sub.cc, for example). If the trench-shaped capacitor retains a high level (V.sub.cc), the potential level of the bit line increases by 1/2 C.sub.s. V.sub.cc caused by charges stored in the trench-shaped capacitor. If the trench-shaped capacitor retains a low level (GND), the potential level of the bit line decreases by 1/2 C.sub.s. V.sub.cc. There is little change in a potential level of the reference bit line during the reading operation, so that the data stored in the memory cell can be read out by detecting the difference of the potential level between the bit line and the reference bit line.
According to the conventional D-RAM, however, there is a disadvantage in that a periodical refreshment of data stored in the trench-shaped capacitor is required to maintain the data, because charges stored in the trench-shaped capacitor is leaked gradually to the semiconductor substrate as the time passes. Furthermore, .alpha.-particles generated in a package encapsulating an IC chip including the D-RAM are irradiated to the memory cells, so that charges of memory cells storing high level information leak through junctions to the substrate. This is a disadvantage called a soft error of cell mode.